Memory/Bus Arbitration in Multiple-Bus Multiprocessor Systems

Abstract

The performance and behavior of tightly-coupled multiple-bus multiprocessor systems have been modeled, developed and evaluated in this I thesis. These systems consists of P processors and M memory modules. Processors and memory modules were interconnected via B global buses, where each bus is connected to all processors and to all memory modules. I The perfonnance of the model is depending on the design of the communication structure between the processors and memory modules. In this I thesis the three types of communication structures are studied; Single-bus, Crossbar, and more general Multiple-bus multiprocessor. The performance of such systems has been measured and evaluated in terms of some popular I criteria, such as effective memory bandwidth, probability of acceptance and number of idle cycles. I Single-bus is the simplest interconnection network for a multiprocessing system, that is a common communication path (bus) connecting all the system components, although the single-bus organization is relatively inexpensive, I two, or more processors can not access the bus at a time. When the system is expanded by adding more processors or memory modules, bus contention I increases and the system performance degrades considerably. So, hardware arbiters are used in order to deal with the conflicts when two or more processors attempt to access the same memory module at the same time. I