Energy Optimization for a Modern Embedded Microprocessor

Abstract

The design power dissipation became a major concern for IC designers as the product success depends on the battery lifetime, cooling management and thermal limits. There- fore, IC designers started to see the impact of power on design speed, design complexity, design area and fabrication cost. CAD tools could support power analysis and power optimization by different methodologies during the automated ASIC design flow. ASIC design flow consists of several steps to design, optimize and verify the IC and a toolset is used for each step. For that purpose some open source EDA tools are developed and used by the students and researchers to learn and fabricate their own Integrated Cir- cuits. This indicates how the EDA tool improvement community is growing in progress and it becomes flexible to design a hardened macro or even system on chip (SOC) with incorporating of these tools. This thesis presents the digital ASIC implementation of RISC-V “DwarfRV32”, which is an open source footprint for RV32I ISA using an open source PDK “sky130A”. The design is implemented using two approaches, which are Openlane flow and Commercial tools. We then compare between the two flows on important parameters like power consumption and timing performance to get the most optimized design. Through all the design flow steps from RTL code to GDSII, each tool has its own methodologies and optimization techniques to get the most optimized design in power consumption, speed and area.