Design of Low Power Circuits for Integrated Power Management Units

Abstract

This thesis aims at studying and design low power circuits to be used for power management units such as low power low-dropout regulators (LDOs). The thesis is divided into two main parts, designing an ultra-low power high power supply rejection (PSR) LDO using adaptive loop gain control, and designing a low-power, improved inrush current, wide-load range and high PSR LDO using feed-forward load-dependent cancellation buffer (FFLCB) and pass device splitting. The thesis consists of five chapters as below, Chapter 1 Chapter 1 gives a brief introduction to the motivation, objectives, major contributions and organization of the thesis. Chapter 2 Chapter 2 presents a literature survey for different LDOs and discusses the prior art for improving PSR and stability. The analysis and design of prior and conventional LDOs are discussed thoroughly in this chapter.