INTERNET OF THINGS HARDWARE SECURITY

Abstract

IoT makes use of data collected from IoT devices to optimize the observation and the control of the world in domains such as logistics, retail, military, and healthcare. The huge and continuously increasing number of IoT devices is leading to more attack vectors by hackers. The IoT devices are extremely vulnerable to attack, as they are tiny, and normally possess intelligence which is enough to perform a single function, so that they can fit almost anywhere. The emergence of the Internet of Things (IoT) applications has made the security issue more critical and complicated As a result, the security becomes one of the main challenges required by IoT stakeholders to deploy the IoT applications in the market.

Authenticated Encryption (AE) and Authenticated Encryption with Associated Data (AEAD) play a significant role in cryptography as they simultaneously provide confidentiality, integrity, and authenticity assurances on the data. The Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR) seeks optimal authenticated ciphers based on multiple criteria, including security, performance, area, and energy-efficiency. Lightweight applications such as smart card, Radio Frequency Identification (RFID), etc. demand low area and low memory footprint. AEAD schemes suitable for implementation in wearables additionally require that the power consumed is as minimum as possible.

The objective of this thesis is to provide a low area low power optimized implementation for cryptography algorithms to match the power constraints imposed by the low power IoT applications. In this thesis low area and low power implementations of selected ciphers from the CAESAR candidates namely NORX, Tiaoxin, SILC, COLM, and JAMBU are provided. The optimization methodology depends on resource sharing as the addressed Ciphers are found to use resource duplication in their implementations. To evaluate the hardware performance of the proposed optimized implementations, pairs of corresponding publicly available HS implementations and proposed Optimized implementations are benchmarked for FPGA and ASIC implementations. A reduction in area with an average of 40% and a reduction in dynamic power with an average of 52% are achieved compared to their corresponding high-speed architectures. Moreover, throughput (TP) in (Mbps) decreases by an average of 70% and throughput-to-area (TP/A) in (Mbps/Slices) decreases by an average of 52%.

Moreover, Partial dynamic reconfiguration is used to achieve resource-efficient and energy-efficient hardware security. Partial Reconfiguration allows for the dynamic change of modules within an active FPGA design. This flow requires the implementation of multiple configurations which ultimately results in full bit streams for each configuration, and partial bit streams for each Reconfigurable Module. Two methodologies were proposed in this thesis to achieve resource-efficient and energy efficient hardware security. The first methodology utilize PDR to implement the crypto processor, the DPR is used to switch the operation mode between encryption and decryption based on one control signal that control the processor either to perform encryption or decryption operation. The methodology was applied on two algorithms COLM and OCB. The methodology reduced the area for COLM by 40% and for OCB by 35%, in addition to reducing the energy for COLM by 33% and OCB by 37%.

The second methodology utilize PDR to switch the cipher based on the message length to achieve energy-efficient hard ware encryption as it was found that The energy Consumed per bit depends on the message length because of the overhead required for Cipher initialization or finalization. The switch is done between Morus and Ascon algorithms, based on the message length the most energy efficient cipher is selected.