High Speed Sigma Delta ADC

Abstract

The thesis showed at first the need for high speed ADCs, and how the continuous time Σ∆ ADCs are a good candidate for high speed applications for their low power and high speed. Then a brief introduction to the Σ∆ ADCs was given and how they evolved from discrete time to continuous time. The thesis then presented a MATLAB based tool which can help in designing the multistage feedforward opamp either 2,3, or 4 stages. The tool can help in determining the required gain and BW of each stage according to the ADC specifications, and then the tool results were verified in CTΣ∆ simulink model (LP and BP) to show the effect of the multistage transfer function on the SNR. A comparison between feedforward and feedback CTΣ∆ were presented, and how these architectures affect the opamp requirements. Also a jitter comparison between single bit, multibit and FIR DACs ( in case of LP) were done to show the trade offs between multibit and single bit. Then 2 design examples were presented, the first one was on 65nm for 3rd order LP CTΣ∆ using 2 taps FIR DAC, system results and simulation results showed that although FIR DACs help in decreasing metasability effect but it increase the opamp requirements (gain and Fu). The ADC uses a 6.4 GHz sampling frequency with OSR of 32, thus it has BW of 100 MHz, the ADC was designed to meet the requirements for various standards (due to its wide BW) up to 5G NR1 which requires 100 MHz BW and more than 70 dB DR (as shown in chapter 4).