Charge Steering Based Phase-Locked Loop Circuits

Abstract

This thesis presents charge-steering based circuit design as an implementation approach for ultra-low power phase-locked loop (PLL) clock generation systems. This design ap- proach is driven by the need for new techniques to minimize the power consumption of a clocking system, especially for wire-line transceivers. In contrast to static current-based design, charge-based design consumes only dynamic power which results in a great re- duction in power. Low-power charge-steering charge pump with current mismatch com- pensation and low-power high-frequency charge-steering frequency divider are proposed for GHz range PLLs. The PLL was designed using CMOS 65 nm technology. It operates at 6 GHz frequency with 100 MHz input frequency. The charge pump consumes 55 µW, and the frequency divider can operate at up to 16 GHz and consumes 170 µW at the PLL frequency. This is less than 50% of the power consumption of the conventional techniques, offering ultra-low-power operation for the PLL.

The thesis is divided into five chapters as listed below:

Chapter 1

This chapter is an introduction, it starts with a brief background, followed by the thesis contribution and outline.