Automated Analog Design Physical Verification
Ahmed Mohamed Mostafa Mohamed Arafa;
Abstract
At the nanometer technology node, analog circuit designers are faced with the problem of reduced voltage supply headroom, increased wiring parasitic resistance (Rp), capacitance (Cp), more restrictive electro- migration (EM) limits on wire widths, and sev
Other data
| Title | Automated Analog Design Physical Verification | Other Titles | آتمتتة التحقق من الرسم التخطيطى للدوائر التناظرية | Authors | Ahmed Mohamed Mostafa Mohamed Arafa | Keywords | Automated Analog Design Physical Verification | Issue Date | 2012 | Description | At the nanometer technology node, analog circuit designers are faced with the problem of reduced voltage supply headroom, increased wiring parasitic resistance (Rp), capacitance (Cp), more restrictive electro- migration (EM) limits on wire widths, and sev |
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