Emulation-based System-on-Chip Verification

Hanan Mohamed Sameh Tawfik;

Abstract


Systems on Chip (SoC) nowadays, have become heterogeneous in nature. They can be composed of a mix of analog and digital components.
In some verification environments, SystemC is used to model the digital components and SystemC-AMS extensions can be used to model the analog components. Later in the verification process, the digital part can be refined to RTL whosesoftware simulation could be quite slow.
As Systems on Chip are becoming more complex, the functional verification of their RTL-level digital components tends to be performed using emulation platforms to verify large designs faster.
In this work, an approach is proposed that enables the interfacing ofSoCs’ digital and analog components in an emulation environment, where the digital components (at the RTL level) would be running on the emulator, while the SystemC-AMS components would be running on the associated emulator host machine. The difficulty of this interfacing lies in the SystemC-AMS being a timed environment with a time wheel completely decoupled from emulation time. A case study that illustrates the feasibility of the proposed interfacing approach is also presented.



Other data

Title Emulation-based System-on-Chip Verification
Other Titles التحقق من وحدات النظام علي الشريحة باستخدام جهاز للمحاكاة
Authors Hanan Mohamed Sameh Tawfik
Issue Date 2017

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