Automated Verification of Digital Systems

Abstract

This research introduces a new methodology for digital design properties extraction from simulation traces. A new Breadth-First Decision Tree (BF-DT) mining algorithm is innovated for complete properties extraction from simulation traces. The new mining engine supports both bit-level and word-level values of different design variables. The contributed mining technique could extract all design properties activated by the simulation traces. Such properties are relating the design output target variables with their corresponding cone of interest feature variables. The new methodology for automatic generation of assertions has been tested for different designs with different sizes. The generated assertions completely match with all design properties covered in the input simulation traces. Moreover, the generated assertions are at the highest possible level of abstraction leading to the best coverage for the input data space. The simulation results show that the proposed methodology has proven superior efficiency in extracting both bit-level and word-level complete assertions of digital design in superior quality, and feasible time and memory consumption.

Keywords: verification, assertion, coverage, mining, decision tree.