VHDL Synthesis for ASICs Applied to DLX RISC Processors
Ibrahim AI-Hanafy AJ-Mohandes;
Abstract
In this thesis, a VHDL synthesizable model for AutoLogic //, is developed for a modified and unpipelined version of the 32-bit DLX RISC processor, called DLXS. Tin's processor is taken as a case study for synthesizing complex digital ASICs with the VHDL l
Other data
| Title | VHDL Synthesis for ASICs Applied to DLX RISC Processors | Other Titles | بناء الدوائر ذات التطبيقات المحدده باستخدام لغه WHDL فى حاله المعالجات DLX RISC | Authors | Ibrahim AI-Hanafy AJ-Mohandes | Keywords | VHDL Synthesis for ASICs Applied to DLX RISC Processors | Issue Date | 1998 | Description | In this thesis, a VHDL synthesizable model for AutoLogic //, is developed for a modified and unpipelined version of the 32-bit DLX RISC processor, called DLXS. Tin's processor is taken as a case study for synthesizing complex digital ASICs with the VHDL l |
Attached Files
| File | Size | Format | |
|---|---|---|---|
| 114134X49.pdf | 668.46 kB | Adobe PDF | View/Open |
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