OPTIMIZING FPGA-BASED HARD NOCS
Sameh Attia Ahmed Attia;
Abstract
Key Words:
NoC; FPGA; Router; BlockRAM
Summary:
In this thesis, we evaluate various NoC design parameters to find the best-fit parameters that can be used in the nonconfigurable hard NoC. We also evaluate different router architectures to select the optimum one for hard NoCs. The designed router reduces the wasted area by using minimum and shareable resources. Moreover, we propose an efficient novel way for embedding the hard NoC inside the FPGA. The proposed NoC provides the FPGA with a high performance communications infrastructure at a negligible cost.
NoC; FPGA; Router; BlockRAM
Summary:
In this thesis, we evaluate various NoC design parameters to find the best-fit parameters that can be used in the nonconfigurable hard NoC. We also evaluate different router architectures to select the optimum one for hard NoCs. The designed router reduces the wasted area by using minimum and shareable resources. Moreover, we propose an efficient novel way for embedding the hard NoC inside the FPGA. The proposed NoC provides the FPGA with a high performance communications infrastructure at a negligible cost.
Other data
| Title | OPTIMIZING FPGA-BASED HARD NOCS | Other Titles | تحسين شبكات الرقائق الإلكترونية الثابتة الخاصة بمصفوفات البوابات المنطقية القابلة للبرمجة | Authors | Sameh Attia Ahmed Attia | Issue Date | 2016 |
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