LOW POWER NANOMETER FPGA DESIGN TECHNIQUES AT THE DEVICE AND CIRCUIT LEVELS
Osama Ahmed Mohamed Ahmed Abdelkader;
Abstract
Key Words:
FPGA; DTMOS; FinFET; Charge recycling; Low power
Summary:
We studied in this work replacing the conventional MOSFETs in FPGA with DTMOS and evaluated FPGA cluster and MUXs based on performance, power, and energy. DTMOS shows better energy for cluster (FPGA logic block), and MUXs (FPGA routing). We also studied using FinFET for technology nodes from 20nm down to 7nm, and also studied the impact of environmental variations on FinFET FPGAs metrics. Finally, we present a novel technique for FPGA power reduction on circuit level, the multiple charge recycling technique shows power saving by 32% in SPICE simulations.
FPGA; DTMOS; FinFET; Charge recycling; Low power
Summary:
We studied in this work replacing the conventional MOSFETs in FPGA with DTMOS and evaluated FPGA cluster and MUXs based on performance, power, and energy. DTMOS shows better energy for cluster (FPGA logic block), and MUXs (FPGA routing). We also studied using FinFET for technology nodes from 20nm down to 7nm, and also studied the impact of environmental variations on FinFET FPGAs metrics. Finally, we present a novel technique for FPGA power reduction on circuit level, the multiple charge recycling technique shows power saving by 32% in SPICE simulations.
Other data
| Title | LOW POWER NANOMETER FPGA DESIGN TECHNIQUES AT THE DEVICE AND CIRCUIT LEVELS | Other Titles | طرق تصميم مصفوفة بوابات منطقية قابلة للبرمجة قليلة القدرة علي مستوي الجهاز والدائرة | Authors | Osama Ahmed Mohamed Ahmed Abdelkader | Issue Date | 2016 |
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