INTERCONNECT SYNTHESIS IN l-JIGII SPEED DIGITAL VLSI ROliTING

Abstract

The advent of the nanotechnology has introduced new challenges and non-conventional problems to High Speed Digital VLSI design. Moreover, the relentless progress of manu­ factucing.technologyJs=widening..the_gap_between_current CAD_tools and V.LSLtechnolo. gies. This is reflected clearly in the IC design process where the IC flow has become very iterative, especially-in the back end phase. This returns to the complexity of placement and routing phases and the inadequate approximations used for interconnect modeling and• characterization. Hence, we introduce a new approach to complete the routing without or with minimal iterations. Instead of employing the traditional flow that uses inaccurate interconnect models and characterization techniques then analyze the output to point out errors in the resulting layout, we propose Interconnect Synthesis as a framework. Within this framework, we introduce an enhanced routing algorithm that outperforms traditional routers and .present a more accurate interconnect modeling and signal characterization techniques for interconnect synthesis. Consequently, the output of the routing-phase will no longer suffer from the errors in the timing or the signal integrity constraints. Finally, the analysis phase will become merely a verification phase, not a process for re-iterations.