FPGA IMPLEMENTATION OF IMAGE AND VIDEO ENCODER/DECODER USING EFFICIENT 3D DISCRETE WAVELET TRANSFORM

Abstract

Image and video compression standards are developing nowadays by utilizing the wavelet transform, which became very important in the data compression field. This thes1s focuses on the hardware implementation of an image encoder and decoder design. A complete design of the Forward Discrete Wavelet Transform (DWT) in the encoder side as well as the design of the Inverse Discrete Wavelet Transform (IDWT) in the decoder side is implemented. It is downloaded on a reconfigurable FPGA hardware. The target platform is one of the FLEX 1OKE family of FPGAs provided by the ALTERA corporation. The encoder/decoder design can be used for wavelet I compression/decompression systems or even as a part of the algoritlm1s to be used in future mobile devices for image encoding/decoding using wavelets. The• design of the image encoder and decoder is based on the multilevel decomposition and reconstruction of the DWT and IDWT, respectively. For choosing the filter structure used in the wavelet filter bank, the Direct FIR filter structure is compared with the transposed form FIR one with respect to clock latency and chip area utilization upon hardware implementation. The transposed form FIR is chosen because it gives better simulation results concerning the mentioned comparison aspects. The VHDL reference design can be easily h1odified to change the filter coefficients. It is also made generic to fit any image size input to the encoder or the decoder of the system. The hardware implementation of an efficient three-dimensional Wavelet Transform (3D-WT) algorithm for video compression on FPGA is also presented. This algoritlm1 performs the temporal decomposition of a video sequence in a more efficient way than the classical 3D-WT algorithm. The algorithm exhibits lower memory demands and lower latencies for the compression and decompression processes than the classical algorithm. This makes the proposed algorithm fits better for real-time processing. Using the proposed algorithm, the chip area utilization is compared at different frame sizes. The VHDL reference design is also made generic to fit for any frame size.