A New Front-End Architecture for RF. Single-Chip Communication Transceivers
Sherif Hassan Galal;
Abstract
In this thesis, a new front-end architecture for RF integrated wireless transceivers was presented. Also, a new variant of Gilbert cell mixer which posses wide input bandwidth and extremely high linearity is designed and simulated.
Different performance measures used to describe the behavior of RF components were described. A theoretical background of noise in communication systems was first presented. Then, other parameters such as sensitivity, ,linearity and dynamic range were investigated along with test setups required to measure these parameters. Finally, a case-study of a complete receiver was analyzed.
An overview on classical and modern receiver architectures was g1ven to emphasize the integration challenges facing these architectures. A common bottleneck in all these architectures is the need for accurate quadrature components for either image rejection or vector demodulation or both.
An analytical and statistical study of RC sequence asymmetric polyphase networks based on Monte Carlo simulation was presented. The study shows that this class of networks represents an efficient wide-band quadrature generators with reduced sensitivity to components mismatch. On the other hand, the same network is capable of highly suppressing image channels in communication receivers without the need for selective RF and IF filters. The degree of image rejection increases as the number of cascaded stages increases.
Finally, a new image-reject front-end which eliminates the need for quadrature components was presented. Another two modified architectures were introduced to alleviate the. problems associated with the basic architecture. A linear high frequency CMOS mixer was introduced that will highly enhance the performance of the image-reject front-end.
The work presented in this thesis can be extended in various ways
Different performance measures used to describe the behavior of RF components were described. A theoretical background of noise in communication systems was first presented. Then, other parameters such as sensitivity, ,linearity and dynamic range were investigated along with test setups required to measure these parameters. Finally, a case-study of a complete receiver was analyzed.
An overview on classical and modern receiver architectures was g1ven to emphasize the integration challenges facing these architectures. A common bottleneck in all these architectures is the need for accurate quadrature components for either image rejection or vector demodulation or both.
An analytical and statistical study of RC sequence asymmetric polyphase networks based on Monte Carlo simulation was presented. The study shows that this class of networks represents an efficient wide-band quadrature generators with reduced sensitivity to components mismatch. On the other hand, the same network is capable of highly suppressing image channels in communication receivers without the need for selective RF and IF filters. The degree of image rejection increases as the number of cascaded stages increases.
Finally, a new image-reject front-end which eliminates the need for quadrature components was presented. Another two modified architectures were introduced to alleviate the. problems associated with the basic architecture. A linear high frequency CMOS mixer was introduced that will highly enhance the performance of the image-reject front-end.
The work presented in this thesis can be extended in various ways
Other data
| Title | A New Front-End Architecture for RF. Single-Chip Communication Transceivers | Other Titles | بناء جديد لواجهة امامية فى مرسل - مستقبل احادى الرقيقة عند ترددات الراديو | Authors | Sherif Hassan Galal | Issue Date | 1999 |
Recommend this item
Similar Items from Core Recommender Database
Items in Ain Shams Scholar are protected by copyright, with all rights reserved, unless otherwise indicated.