Transmitter design for high speed serial links

Abstract

This thesis presents a multi-standard transmitter design for high speed serial link appli- cations. The target of the design is to achieve a dissipate power less than 1.25 pJ/bit whilereailizingallthestandards’requirements. The choice of multi-standard design is driven by the needs of the industry. With the evolution of I/O market, the time-to-market has become a crucial aspect in the market. Developing an IP for each standard can be a setback for fabless companies to meet the needs of many customers. However, the presence of a single IP that answers the need for all customers can achieve the required can prove to be cost and time efficient. The design of multi-standard transmitters can be challenging for many reasons. First the varying output swing poses challenges on using voltage mode drivers. On the other hand, using current mode drivers can increase the power to almost 4 times of the voltage mode power. Other challenges include the different width’s of the input parallel words and different equalization configurations. A literature survey has been made to review the possible solutions that can be used to design thetransmitter. The standard requirements were carefullyreviewed. The systemrequirementswerederived from the standards’ requirements. Then a system model has been implemented and simulated to validate its performance. The circuits were then implemented relying on some of the solutions from the literature survey and some innovative ideas.