Implementation of high performance digital Electronic circuits for Recognition, Segmentation and Verification at LHC

Abstract

The Compact Muon Solenoid (CMS) is a particle detector, based at CERN in Switzerland, designed to look for new physics. The CMS muon system is designed to provide robust, redundant and fast identification of the muons traversing the system, in addition to trigger capabilities and momentum measurement. For the initial phase of CMS muon system, three types of gaseous detection technologies have been chosen: Drift Tube Chambers (DTs), cathode strip chambers (CSCs), Resistive Plate Chambers (RPCs) and new upgrade Gas Electron Multiplier (GEM). This thesis is concerned with the digital readout electronics for the GEM detector where a specific algorithm has been implemented using Field Programmable Gate Array (FPGA) device for processing signals generated from a front-end electronic board of the GEM detector. This algorithm is executed for processing (i.e. recognition, segmentation and verification) digital signals taken from the detector front-end electronic board. Such a processed signal is then analyzed by feeding it as an input to a data acquisition system (DAQ). Set of VHDL and Verilog hardware description language codes were also created to implement this algorithm using a regular FPGA hardware device.