FPGA-based Design and implementation of True Random Number Generator & Public key system co-processor
Fatma El-Zahraa Fouad Mahmoud;
Abstract
In this thesis a complete design and implementation of a true random number generator and a public key system co-processor is presented.
The implementation 1s realized on single FPGA chip (Xilinx Virtex II Pro
XC2VP30).
The TRNG type is chosen specifically to be suitable for FPGA implementation (oscillator phase noise type). Unlike similar implementations, the realization of it is completely done on hardware; this increases the reliability, and level of secrecy. Also, this makes the implementation more suitable for cryptographic applications.
The public key co-processor provides public key systems (RSA, EL-Gamal, Rabin,..., and others) with their basic and needed repeatedly mathematical operations (multiplication of two large numbersl024 bits in size, modular reduction of 2048 bits numbers to 1024 bits in size, modular multiplication 1024 bits number for multiplicand and modulus, and modular exponentiation of 1024 bits number to exponent up to 1024 bits).
The inputs entered in 16 bits words, outputs from public key co-processor are
16 bits words, output from the TRNG modulae is 1 bit.
The design achieved 11.778 MHz on the targeted chip ( XC2VP30, package ff896, speed grade -5). The device utilization for the two implemented modules is 1% of the chip resources for the TRNG module and 78% of the chip resources for the co processor module.
The implementation 1s realized on single FPGA chip (Xilinx Virtex II Pro
XC2VP30).
The TRNG type is chosen specifically to be suitable for FPGA implementation (oscillator phase noise type). Unlike similar implementations, the realization of it is completely done on hardware; this increases the reliability, and level of secrecy. Also, this makes the implementation more suitable for cryptographic applications.
The public key co-processor provides public key systems (RSA, EL-Gamal, Rabin,..., and others) with their basic and needed repeatedly mathematical operations (multiplication of two large numbersl024 bits in size, modular reduction of 2048 bits numbers to 1024 bits in size, modular multiplication 1024 bits number for multiplicand and modulus, and modular exponentiation of 1024 bits number to exponent up to 1024 bits).
The inputs entered in 16 bits words, outputs from public key co-processor are
16 bits words, output from the TRNG modulae is 1 bit.
The design achieved 11.778 MHz on the targeted chip ( XC2VP30, package ff896, speed grade -5). The device utilization for the two implemented modules is 1% of the chip resources for the TRNG module and 78% of the chip resources for the co processor module.
Other data
| Title | FPGA-based Design and implementation of True Random Number Generator & Public key system co-processor | Other Titles | تصميم مولد للأرقام العشوائية الحقيقية ومعالج مساعد لأنظمة التأمين باستخدام المفتاح العام وتنفيذهما على FPGA | Authors | Fatma El-Zahraa Fouad Mahmoud | Issue Date | 2007 |
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