HARDWARE ACCELERATION OF STREAM CIPHER SECURITY ALGORITHMS USING DYNAMIC PARTIAL RECONFIGURATION DPR AND SDSOC TOOLS

Abstract

With the spread of the fourth industry revolution applications which includes many smart devices like Robots, cloud systems, IoT, cyber security...etc, data security has become one of the most important topics that the world are focuses on it due to the huge amount of data that needs to be transferred from point to point on these applications. Data security means protecting data from corruption or from being disclosed from unauthorized users. This thesis presents different implementations techniques to accelerate stream cipher security algorithms which provide both confidentiality and integrity for a variable length of data. The implementation techniques provided in this thesis are implementation using SDSoC tool, implementation using DPR technique and implementation using both SDSoC and DPR at the same time.