EXTRACTION & MODELING FOR MULTIGATE TRANSISTOR PARASITICS

Abstract

In VLSI applications, the parasitic capacitance between signal lines can deplete our whole design. At low frequencies, parasitic capacitance is usually ignored, but in high frequency circuits, it can be a major problem. For example, in amplifier circuits with extended frequency response, parasitic capacitance between the output and the input can act as a feedback path, causing the circuit to oscillate at high frequencies. These unwanted oscillations are called parasitic oscillations. The parasitic capacitance arises from an electrical coupling between one signal line and another signal line or a signal line and the substrate. In some designs, it becomes mandatory for us to reduce the parasitic capacitance of a particular electrical path with respect to other signals. In this thesis, we introduce numerical simulations of this parasitic capacitance and the effect of changing different geometrical parameters of the FinFET transistor on parasitic capacitance. Numerical simulations takes a long time, hence they are not suitable for VLSI design due to the large number of transistors that exists within the design. Hence, the introduction of a compact model becomes a necessity. The starting models used in this thesis needed adjustments to properly model multi-fin FinFET transistors. We verify the accuracy of the model by performing 3D numerical simulations using Calibre® xACT 3D, then performing parameter extraction and fitting. The structures used are triple-gate FinFETs, with the technology file being that of a world-renowned fab in Taiwan. These modifications improved the accuracy of the compact model to reach 2%

Key Words: FinFETs, Parasitic Capacitance, Parameter Extraction, Modelling, Fringing Gate Capacitance.