Low Power Constellation De-mapping Design for DVB-T2 Standard
Nourhan Mohamed Mohamed Bahgat;
Abstract
This Thesis presents low power consumption that is a key parameter in most electronics applications. While performance and area remain to be two major design goals, power consumption has become a critical concern in today’s VLSI system design. Some of low power techniques controlled by designers and the other techniques are out of the scope of designers, since they would need to act on a rank of below gate level.
Also, presents prior work in de-mapper design and proposed design of DVB-T2 rotated constellation de-mapper. Focus on importance of rotated constellation. The proposed de-mapper combines between projections based de-mapping technique and approximation of the Euclidean distance computation. There are four schemes based on projection de-mapping for decision. Scheme C (all-bits comparison) is adopted for the proposed de-mapper implementation since it demonstrated the best BER performance that matches the reference performance of all-bits LLR de-mapping.
The design benefits from projection based de-mapping to significantly reduce power by saving LLR calculations. It also used several techniques to be even more energy efficient. Experimental results clearly indicate there is no performance degradation when projection based de-mapping is used as shown in previous chapter. Experimental results indicate significant reduction of LLR calculations and corresponding energy saving as Eb/N0 increases. The proposed design will be highly useful in low power DVB-T2 receivers. New energy efficient design of the DVB-T2 constellation de-mapper prototyped by VHDL with embedded processor microblaze. The idea and implementation technique can be easily extended to apply to any rotated constellation de-mapper.
Also, presents two algorithms to convert from the hybrid output stream from proposed de-mapper to all-soft stream in order to guarantee the best performance of the soft LDPC decoder. These two algorithms were tested and give almost the same performance at low SNR values and a slightly better performance at a moderate SNR range so, the proposed design of statistical LLR assignment utilize single-sided standard deviation. This proposed design prototyped by VHDL. The proposed full system saves almost 36 % from energy when LLR calculation is skipped and saves hardware almost 22% more than comparison work.
6.2 Future work
The idea and implementation technique can be easily extended to apply to any rotated constellation de-mapper. The future plan of this research is studying Hardware Implementation of FEC decoder (LDPC and BCH). Hardware implementation of iterative receiver structure for the BICM scheme.
Also, presents prior work in de-mapper design and proposed design of DVB-T2 rotated constellation de-mapper. Focus on importance of rotated constellation. The proposed de-mapper combines between projections based de-mapping technique and approximation of the Euclidean distance computation. There are four schemes based on projection de-mapping for decision. Scheme C (all-bits comparison) is adopted for the proposed de-mapper implementation since it demonstrated the best BER performance that matches the reference performance of all-bits LLR de-mapping.
The design benefits from projection based de-mapping to significantly reduce power by saving LLR calculations. It also used several techniques to be even more energy efficient. Experimental results clearly indicate there is no performance degradation when projection based de-mapping is used as shown in previous chapter. Experimental results indicate significant reduction of LLR calculations and corresponding energy saving as Eb/N0 increases. The proposed design will be highly useful in low power DVB-T2 receivers. New energy efficient design of the DVB-T2 constellation de-mapper prototyped by VHDL with embedded processor microblaze. The idea and implementation technique can be easily extended to apply to any rotated constellation de-mapper.
Also, presents two algorithms to convert from the hybrid output stream from proposed de-mapper to all-soft stream in order to guarantee the best performance of the soft LDPC decoder. These two algorithms were tested and give almost the same performance at low SNR values and a slightly better performance at a moderate SNR range so, the proposed design of statistical LLR assignment utilize single-sided standard deviation. This proposed design prototyped by VHDL. The proposed full system saves almost 36 % from energy when LLR calculation is skipped and saves hardware almost 22% more than comparison work.
6.2 Future work
The idea and implementation technique can be easily extended to apply to any rotated constellation de-mapper. The future plan of this research is studying Hardware Implementation of FEC decoder (LDPC and BCH). Hardware implementation of iterative receiver structure for the BICM scheme.
Other data
| Title | Low Power Constellation De-mapping Design for DVB-T2 Standard | Other Titles | تصميم منخفض الطاقة لعكس التمثيل الكوكبى وفقا لمعيار التليفزيون الرقمى الأرضى من الجيل الثانى DVB-T2 | Authors | Nourhan Mohamed Mohamed Bahgat | Issue Date | 2015 |
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