LayoutDependentEffects onNanometer IC Designs AThesis

Abstract

AsVLSItechnologypushesintousingadvancednodesdownto7nmandbe- low,designersandfoundrieshaveexposedtoasignificantsetof yieldprob- lems.Tocombatyieldfailures,thesemiconductor industry hasdeployed newtoolsandmethodologiescommonlyreferredtoasdesignformanufac- turing(DFM). Mostof theearlyDFMeffortsconcentratedoncatastrophic failures,orphysicalDFM problems.Howeveranewareaofyieldfailures arenowrelatedtoreliability andperformanceofthemanufacturedcircuits, andhavingincreasedemphasisonwhatisnowcalled“Parametric Yield” issues,andsometimesreferredtoaselectrical-DFM(eDFM).

Thisthesispresentstheparametricyieldproblemsduetophysicallayout parameterseffectsonthefinalcircuit performance,with morefocuson theireffectsonAnalogandMixedsignal(AMS)integratedcircuits(ICs). TheselayouteffectsaregenerallyknownasLayoutDependentEffectsor (LDEs). Theseparametershavetobeconsideredinthedesigncycleandto bebackannotatedintotheschematicsorlayoutforaccuratesimulations. ThesispresentsacompleteeDFMsolutionthatdetects,analyzes,andfixes electricalhotspots(e-hotspots)withinananalogcircuitdesign,thosecaused bydifferentprocessvariations.Novelalgorithmsareproposedtoimplement theenginesusedtodevelopthissolution.TheflowisgrantedaUSpatented asof2014.

Thesolutionisexaminedondifferentdesigns,andatdifferenttechnology nodes,includinga130-nmparametrically-failinglevelshiftercircuitusedin USBIP,whichisverifiedwithsiliconwafermeasurementsthatconfirmthe

existenceofparametricyieldissuesinthedesign.Additionalexperiments areappliedona65-nmindustrialoperationalamplifierandvoltagecontrol oscillator(VCO), aswellas45nmdigital standardcelldesign.E-hotspot deviceswithhighvariationsindccurrentareidentified.Afterfixingthee- hotspots,thevariationsinthesedesignsaredramaticallyreducedtowithin designer’sacceptancecriteria,whilesavingtheoriginalcircuitspecifications.