DYNAMIC PARTIAL RECONFIGURATION VERIFICATION AND APPLICATIONS ON FPGA DEBUGGING

Abstract

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows a portion of the logic to be reconfigured at runtime while the rest of the logic keeps operating. Such category of designs called Dynamically Reconfigurable Systems (DRS) designs. This feature enables the designers to build complex systems such as Software Defined Radio (SDR) in a reasonable area. Despite of the flexibility provided by the DPR, there are new challenges to design and verify the designs which utilize the DPR technique when it is compared to static FPGA systems.