HARDWARE IMPLEMENTATION OF A SIMPLIFIED RADIX-4 SUCCESSIVE CANCELLATION DECODER FOR POLAR CODES
Hussein Galal Hussein Hassan;
Abstract
In this thesis, we proposed a latency reduced decoder for the polar
codes, this decoder is based on the successive cancellation decoding. The
main idea is based on the usage of a radix-4 processing unit to calculate
intermediate LLR values, a new last stage processing unit that is capable
of decoding more than 4 bits in a cycle and the usage of the partial sum
lookahead technique to improve hardware utilization and decrease the
overall latency
codes, this decoder is based on the successive cancellation decoding. The
main idea is based on the usage of a radix-4 processing unit to calculate
intermediate LLR values, a new last stage processing unit that is capable
of decoding more than 4 bits in a cycle and the usage of the partial sum
lookahead technique to improve hardware utilization and decrease the
overall latency
Other data
| Title | HARDWARE IMPLEMENTATION OF A SIMPLIFIED RADIX-4 SUCCESSIVE CANCELLATION DECODER FOR POLAR CODES | Other Titles | تنفيذ دائرة فك تشفير للشفرات القطبية باستخدام الالغاء المتتالي المبسط ذو اساس رباعي | Authors | Hussein Galal Hussein Hassan | Issue Date | 2018 |
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