Analog Layout Router for Sub-nm Manufacturability

Abstract

The EDA solutions made to facilitate the work of analog designers are very limited and outdated. This was due to the focus given through the last decades for digital circuits in accordance with Moore’s law. Also, the fact that analog design is very sensitive to various effects and involves multiple designing constraints that are not found in its digital counterpart. Analog design is of a heuristic nature and knowledge intensive. Luckily, with more reports on how analog design has become the bottle neck of IC design, now, EDA companies are shifting their focus and intensifying their efforts to automate Analog circuit design. Analog design consists primarily two paths, top-bottom electrical path and bottom-up physical path. The physical path consists of layout generation and verification. Layout generation has reported to cause nearly 30% deviation of the electrical results in small nodes (20 nm and below). Hence, it is of very critical importance to seek automation solutions for the layout generation problem. The thesis is divided into five chapters in addition to the lists of contents, tables and figures as well as list of references and one appendix.:

• Chapter 1: Introduction to Analog Circuit Layout Generation o Presents a brief introduction to the area of analog IC design automation, with special emphasis to the automatic layout generation. • Chapter 2: Literature Review on the-State-of-the-Art Solutions o Present the placement and routing problem in the EDA and a brief overview of the most recent tools developed in this field. • Chapter 3: Proposed Automation Flow o Gives an overview of the proposed automatic flow for analog IC design, with emphasis on the layout generation task • Chapter 4: Results & Discussions o The flow will be demonstrated on a differential operational transconductance amplifier “OTA”