Digital enhancement of frequency synthesizers
Ouda, Mahmoud; Hegazi, Emad; Ragai, Hany F.;
Abstract
In this paper, we propose an All-Digital On-Chip Phase Noise Measurement Technique. This Technique can be integrated as part of a built-in self-test (BIST) scheme for phase-locked loop (PLL)-based clock synthesizers. The proposed technique based on an all digital ΣΔ-frequency discriminator. Unlike all previously reported techniques, our proposed technique is implemented using digital-only circuits and can report digital numbers corresponding to the close in phase noise level of the PLL to a digital BIST controller. This makes it easily integrated and scaled down for high-density microprocessor applications with modern sub 100nm technology nodes. ©2010 IEEE.
Other data
| Title | Digital enhancement of frequency synthesizers | Authors | Ouda, Mahmoud; Hegazi, Emad ; Ragai, Hany F. | Keywords | All digital PLL (AD-PLL) | Jitter | Phase domain | Phase noise | PLL | Sigma delta frequency discriminator (ΣΔFD) | Voltage-controlled oscillator (VCO) | Issue Date | 31-Aug-2010 | Journal | ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | ISBN | 9781424453085 | DOI | 10.1109/ISCAS.2010.5537384 | Scopus ID | 2-s2.0-77956007349 |
Recommend this item
Similar Items from Core Recommender Database
Items in Ain Shams Scholar are protected by copyright, with all rights reserved, unless otherwise indicated.