LOW-NOISE WIDE-BANDWIDTH PHASE-DOMAIN ALL-DIGITAL FRACTIONAL-N PHASE-LOCKED LOOP

Abstract

In this thesis, an ADPLL that employs a high-resolution TDC and a high- linearity DTC to achieve low in-band phase noise and spurs with wide bandwidth and low power consumption is presented. The TDC/DTC set is implemented in TSMC-40nm CMOS process. A time-amplifier based TDC (TA-TDC) is utilized to achieve a sub-gate delay resolution of 3.2 pS. The TA-TDC achieves an integral nonlinearity (INL) less than 0.5 LSB and power consumption of 108 uW. A constant-slope DTC (CS-DTC) that leverages the concept of charge redistribution is proposed. The CS-DTC achieves 0.3 LSB INL. Consequently, a fractional spur of level better than -48 dBc/Hz is expected at the PLL output. The DTC achieves 1.7 pSrms integrated jitter which dominates the in-band phase noise of the PLL. The CS-DTC consumes only 8 uA from 1.1 V supply. The PLL was able to achieve 1.44 MHz bandwidth at 2.5 GHz output frequency using 50 MHz reference. The PLL achieves better than -106 dBc/Hz in-band phase noise which translates to an integrated RMS-jitter of 682 fS.