Low Power Circuits for High Speed Serial Links Transceivers

Abstract

The thesis is divided into five chapters as listed below: Chapter 1 This chapter introduces the dissertation and discusses the motivation for this work, followed by the thesis outline.

Chapter 2

This chapter provides a background to the topic, illustrating the operation and compo- sition of serial link transceivers. It also includes a literature survey on the various types of the clock and data recovery (CDR) systems. In addition, a classification of the CDR systems based on the literature survey is provided. The CDR systems are classified according to the existence of feedback, the type of phase detectors (PD), the existence of reference clock and the method of its implementation.

Chapter 3

This chapter illustrates the linear models for each block in second-order BBPD-CDR including a newly proposed model for the decimator block. It also describes the full linear model of CDR used to calculate the jitter-transfer (JTRAN ) and jitter-generation (JGEN ). In addition, a derivation of an equation for calculating the jitter tolerance of the 2nd order digital BBPD based CDR and a description of the operation of conventional decimation topologies and their effect on CDR systems’ performance are provided.

Chapter 4

This chapter compares the most commonly used decimation topologies in CDR systems. It also provides an intuitive explanation for their effect on CDR jitter performance. The chapter also introduces a novel decimation topology to enhance the jitter performance of the CDR. In addition, the chapter describes the operation of conventional PI and focuses on the drawback of trigonometric PI (TPI) as well as linear PI (LPI). It also proposes a novel PI to handle the major issues in common PI designs and enhance the PI phase update rate

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