Formal verification of digital circuits by 3-valued simulation
Wahba, Ayman; Aas, Einar J.;
Abstract
A new technique for digital circuit verification is presented. The new technique is based on the 3-value simulator, 3VS. Our motivation for utilizing 3VS is the desire to bridge the gap between common industrial practice of verification through simulation, and the world of formal verification. A metric for verification coverage is defined, and it is shown to provide a lower bound of design confidence. 3VS and OBDD-based formal verification are compared, and none of the methods is declared generally superior. © 2001 IEEE.
Other data
| Title | Formal verification of digital circuits by 3-valued simulation | Authors | Wahba, Ayman ; Aas, Einar J. | Issue Date | 1-Dec-2001 | Journal | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems | Conference | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems | ISBN | [0780370570, 9780780370579] | Scopus ID | 2-s2.0-77956856584 |
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