Complete Properties Extraction from Simulation Traces for Assertions Auto-generation

Abstract

Machine learning techniques based on Data Miningare employed for automatic assertion generation in hardwaredigital design verification. This paper presents a new miningtechnique to extract all design properties from simulation traces.The extracted properties cover all possible design assertionseither at system level or Register Transfer Logic (RTL)verification depending on the simulated design level. It canafterwards be tuned or filtered to match a certain desiredabstraction level. The new technique is based on a Breadth-FirstDecision Tree (BF-DT) search algorithm. The innovatedalgorithm maps the input simulation traces to a search tree thatcovers all possible input combinations, and prunes the redundantpaths. The proposed technique is tested against recentlyinnovated mining techniques for some basic digital designfunctions as a proof of concept for the gained efficiency. Themain advantage of the new technique is the possibility to extractall the design properties from the simulation traces achievinghundred-percent coverage in a reasonably efficient time formillions of simulation traces.