Method for automatic design error location and correction in combinational logic circuits

Abstract

We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosis-oriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size.