AUTOMATIC TEST PATTERN GENERATION FROM HIGH LEVEL SPECIFICATIONS

Abstract

Tools developed for automatic test pattern generation require the circuit to be described in the form of a netlist. ATPG tools that accept circuits described in a high-level description language, such as VHDL, and generate the required test vectors, are very rare. We present here a new tool that performs ATPG directly from VHDL behavioral descriptions. Performance analysis shows that the patterns generated by our behavioral ATPG tool achieve high fault coverage when tested on benchmark circuits.