FPGA-based low-level CAN protocol testing
Mostafa, M.; Shalan, M.; hammad, sherif;
Abstract
The paper proposes a new approach for testing a CAN bus at the bit-level. It depends on generation of bus errors to cover crucial corner cases. The design makes it possible to go beyond regular frame level testing that is provided by many commercial tools. It goes deep in bit-stream level testing and injection. The proposed design is verified using an FPGA system on chip. Verification results are good against design requirements. © 2006 IEEE.
Other data
| Title | FPGA-based low-level CAN protocol testing | Authors | Mostafa, M.; Shalan, M.; hammad, sherif | Keywords | Automotive testing | CAN | FPGA | Issue Date | 1-Dec-2006 | Journal | Proceedings the 6th IEEE International Workshop on System on Chip for Real Time Applications Iwsoc 2006 | ISBN | [1424408989, 9781424408986] | DOI | 10.1109/IWSOC.2006.348233 | Scopus ID | 2-s2.0-46249131265 |
Recommend this item
Similar Items from Core Recommender Database
Items in Ain Shams Scholar are protected by copyright, with all rights reserved, unless otherwise indicated.